
PCI CD/CDa Configurable DMA Interface User’s Guide Generating an Output Clock
EDT, Inc. May 2007 11
The formula for calculating the output frequency is:
f
out
= (N * V * f
xtal
) / (m * R * H * L * X * 2)
Figure 1. Setting the Output Clock Frequency
For example, for an output clock of15 MHz using a PCI CD-20 (f
xtal
= 10 MHz), the following numbers
work, although they are not unique: N=60, V=1, M=10, R=2, H=1, L=1, X=1
For an output clock of 125 Hz in a PCI CD-20 (f
xtal
= 10 MHz): N=50, V=1, M=10, R=8, H=5, L=50,
X=100
The output clock has a wide range of values, but the frequency limitations at different stages limits the
ultimate ability to exactly reach any specific frequency.
For example, the PLL reference frequency can be as low as 200 KHz, which would seem to allow steps
of 200,000 in the VCO output. Unfortunately, since the maximum VCO output is 50 MHz and the n-
programmable divider only goes to 127, the loop cannot lock unless V is set to 8, giving 1.6 MHz
minimum steps. If, however, R is set to 8, we can get 200 KHz steps at f
xilinx
. The lowest frequency in
this case is at N=32 (6.4 MHz) to N=127 (25.4 MHz), in 200 KHz steps.
The following three library routines, documented in the EDT DMA Software Library, help compute the
output clock frequency:
edt_find_vco_frequency
Computes the phase-locked loop parameters necessary to match or approximate
the supplied target frequency.
edt_set_pll_clock
Sets the phase-locked loop circuit to the value computed by
edt_find_vco_frequency. Includes debugging information.
edt_set_out_clock
Sets the phase-locked loop circuit to the value computed by
edt_find_vco_frequency. Does not include debugging information.
crystal
oscillator
ref divider
M=3 to 127
VCO output div
R=1,2,4, or 8
feedback prescale
V=1 or 8
feedback div
N=3 to 127
f
ref
f
fback
VCO
f
vco
f
xilinx
high-speed odd div
H=1,3,5, or 7
f
low
1st divide by n
L=1–64
2nd divide by n
X=1–256
divide by 2
for clock symmetry
f
out
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