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Hardware Interface Protocol PCI CD/CDa Configurable DMA Interface User’s Guide

14 EDT, Inc. May 2007

Signals

The hardware flow control protocol assumes that FIFO or memory buffers on both ends implement

almost-full and almost-empty thresholds. Therefore, when a BNR (board not ready) or DNR (device

not ready) signal is sent to the transmitting device, the receiver can still accommodate enough data to

allow for cable delay and synchronization.

Table 1. Signals

Signal I/O Description

DAT(15:0) I/O Sixteen bidirectional data lines for DMA data.

STAT(3:0) I Four general-purpose control inputs. Any can be enabled to interrupt the PCI bus

host.

FUNCT(3:0) O Four general-purpose program control outputs. Can be used to reset the user device

or indicate DMA direction for bidirectional devices.

SENDT O Send Timing is a constant clock driven by the DMA interface that the user device can

use (though it need not) to generate the receive timing. See Table 2 for timing

specifications. The source for SENDT can be either:

• the internal oscillator (the default when using pcd_src.bit);

• the signal RXT when the PCI CD is using pcd_looped.bit, or the PCI CDa has

set bit 1 (SELRXT) in the Interface Configuration Register; or

• the PLL when the PCI CD is using pcd_src.bit, or the PCI CDa has set bit 7,

PLLCLK, in the Funct Register.

RXT I Receive Timing is an input to the DMA interface. This is the clock used to synchronize

input data and control signals. This signal can be equal to or less than the SENDT

frequency of the board in use. It is best, although not required, that this signal is a

continuous clock. Data clocked into the DMA interface must propagate through

pipelining registers before it can be transferred into PCI bus memory. If the RXT clock

stops, data is left in this pipe instead of being transferred to host memory.

TXT O Transmit Timing is an output from the DMA interface. TXT synchronizes the DMA

output data and control signals. TXT is an inverted copy of SENDT, which provides

maximum setup and hold on rising edge.

IDV I Input Data Valid is asserted by the device synchronous with RXT, to tell the DMA

interface that data on the DAT(15:0) signals are valid and must be registered and

transferred to the PCI bus memory. The DMA interface will accomplish this unless the

BNR signal has been asserted for >32 IDV signals.

BNR O Bus Not Ready is asserted by the DMA interface synchronous with TXT when 32 bytes

or fewer of data space remains for input data from the device. This warns you to stop

the data transfer or prepare for overflow.

OUTPUT

DISABLE

I Disables the data outputs when more than one PCI CD board is connected to the

same cable. In order to use this signal, you must set the Enable Output Control bit in

the Stat Polarity Register. TTL-compatible. PCI CD only.

ODV O Output Data Valid is asserted by the DMA interface when it has placed valid output

data on DAT(15:0). ODV is asserted synchronously with the TXT clock, and only if

the DNR signal is not asserted.

DNR I Device Not Ready is asserted by the device synchronous with the RXT clock when the

user device is about to run out of space for storing data from the DMA interface. The

amount of overrun buffer required in the device varies according to the cable length.

The PCI CD/CDa may produce four or more words of valid data after DNR is

presented to the input pins.

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 39 40

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